1. Field of the Invention
This disclosure relates to memory, and, more particularly, to register file design.
2. Description of the Related Art
In today's computer systems, there are various levels of storage devices. These various levels of storage support different needs. For example, one need in some computer systems is the need for mass storage that are relatively low priced. This need is frequently met by large, inexpensive fixed-disk storage devices. The tradeoff for these large, inexpensive fixed-disk storage devices is that these devices have slow access times.
In comparison, there is, at times in certain systems, a need for memory devices that can provide very quick access for the reading and/or writing of data. A type of such memory devices is referred to as register files, which are often on the same die as a processing unit that accesses them, as they are accessed very frequently. In addition to quick access times, preferably, these devices are robust, and consume low power.
FIG. 1 illustrates a read portion of a prior art dynamic register file design. In this example, eight data cells 140 are multiplexed to support a dynamic local bit line 110. A clock signal 122 is used to precharge the dynamic local bit line 110 to a known value through transistor 124. Keeper circuit 130 is utilized to “keep” the precharged value on the dynamic local bit line 110 during an evaluation phase of a register file access. During the evaluation phase, for a set of eight data cells 140 possibly containing a data value to be “read”, one of the read enable lines 142 may be used to enable the read of a corresponding data value 141. Upon the assertion of a read enable line 142, a corresponding stored data value may be driven on the local bit line 110. If no read enable line 142 is enabled for the set of eight data cells 140, the keeper circuit 130 is utilized to retain the precharged value on the local bit line 110. The local bit lines are then utilized to drive a subsequent multiplexing circuit to form a global bit line (not shown).
Applicants have recognized a number of conflicting requirements for efficient and/or effective implementations of such dynamic designs, especially in a new generation of high operating frequency integrated circuits. For example, in order to minimize the evaluation time and thus increase the operating frequency, it is desirable to use low threshold voltage transistors for transistors 144 and 148. However, leakage of current through transistors 144 and 148 will affect the robustness of this prior art design. Since lower threshold voltage transistors are more susceptible to leakage, they can not be employed without addressing their susceptibility. Leakage is undesirable as it may cause erroneous evaluations if too much charge is lost. In contrast, using high threshold voltage transistors results in an unacceptably long read delay as the increased threshold voltages increase response times.
Keeper circuits have been used to increase the robustness of the dynamic local bit line design. Keeper circuits are utilized to maintain the precharged value on the dynamic local bit line 110 in cases where low threshold voltage transistors 144 148 may otherwise allow the improper discharge of the precharged value via leakage current. In order to maintain the prechared value on the local bit line, an upsized transistor 132 is utilized as part of the keeper circuitry 130. However, this upsized keeper also results in a read delay that may be unacceptable for the next generation's high operating frequencies.
Thus, a register file design that is robust, while still being able to operate at high operating frequencies is desired.